1. Field of the Invention
Most digital transmitter devices utilize separate frequency-reference sources (e.g., crystal oscillators, SAW resonators, etc.) to determine the various parameters of transmission such as RF carrier frequency, data-transmission bit (baud) rate, data-burst timing, and interface data rates (e.g., serial data input speeds). Even in frequency-synthesized units, one or more crystals are invariably used to set not only the carrier center frequencies, but also channel step sizes and the like. In digital systems incorporating data-acquisition functions, the required A/D converters are often run at independently selected rates dictated by the specific application. Additionally, in the typical modern system implementations employing embedded microprocessors or microcontrollers, there is also a separate clock used to drive the processor which is based on the chip's instruction-cycle times.
As a result, there are usually a multiplicity of relatively unrelated clocks running in the unit which can generate varying levels of mutual interferences due to the “beat” or difference in frequencies between the sources. This problem can be particularly troublesome when clock signals cross-couple via capacitive or radiating means into sensitive low-level analog signal inputs, synthesizer loop-control lines (causing spurious RF emissions), or modulation-signal wiring (causing modulation noise, instabilities, or nonlinearities).
Interestingly, the solution to the aforementioned problem of multiple unrelated clocks and the resultant variable noise and “beat” interactions—fully synchronous system clocking—can also produce a major performance benefit in the implementation of digital data receivers for lower-quality channels. Since virtually all data streams are organized with integrally related numbers of data bits, words, frames, and burst lengths, the fixed, well defined relationships between these rates or frequencies can be exploited to provide additional mechanisms to achieve faster and more robust synchronization to these components, both in acquisition and tracking contexts.
2. Description of Related Art
There are a large number of patents, textbooks, and articles in the literature devoted to the general subject of phase-locked loop (PLL) technology. There have been dozens of patents issued on various aspects of the PLL, including a variety of circuits for loop phase detection, both analog and digital in implementation. The particular aspect of PLL technology considered herein is the performance of PLLs in receiver synchronization, especially in the noisy or distorted-channel conditions (e.g., interference, fading, and/or multipath scenarios) which are far more characteristic of real RF links than the highly idealized case of simple additive white Gaussian noise (AWGN). Invariably, RF circuits are initially analyzed for their performance in a pure AWGN channel due to the simpler (statistical) mathematics; see, for example, Digital Communications, Third Edition, by John G. Proakis, 1995. The performance (i.e., bit error rate versus signal-to-noise ratio) of most demodulators in fading and multipath (dispersive) environments is substantially worse than in pure-AWGN channels, is much more difficult to analyze, and in practice requires significantly more finesse to achieve good link performance. Indeed, most of the mathematical simulations of fading channels are made assuming perfect receiver synchronization is somehow achieved; unfortunately, this in reality is unjustifiably optimistic. At low signal-to-noise ratios (SNRs), synchronization quality can become a dominant factor in the overall receiver bit error rate (BER) performance level. Thus, improved methods of receiver synchronization for use in poorer-grade RF communications channels are needed to elevate wireless system BER performance levels, provide more uniform coverage (particularly in rough terrain), and accommodate greater numbers of users. A survey of the existing patent art will further clarify this need.
U.S. Pat. No. 4,091,331, issued May 23, 1978 to Hans-Peter Kaser, et al, discloses a method to compensate RF carrier phase errors by tracking the carrier with a feedback loop incorporating a phase-error predictor. A means for optimizing the gain of the phase-estimator loop circuit is provided by processing the successive bit-by-bit residual phase errors (Δφn, Δφn+1). This patent describes an adaptive-gain algorithm to optimize the phase tracking of a receiver during changing reception conditions, where the ratio of carrier phase jitter to Gaussian noise is varying due to dynamic RF transmission channel characteristics. If successive phase-error variance samples are uncorrelated (i.e., avg[Dfn,Dfn+1]=0) the loop gain is optimum; if the correlation result is >0, then the loop gain must be increased; and if the correlation is <0, the gain must be reduced. This patent clearly does not describe multiple interconnected phase detectors or PLLs; it therefore has no bearing on the instant invention.
U.S. Pat. No. 5,251,237, issued Oct. 5, 1993 to Alfred Baier, discloses a method of dynamic channel data-quality assessment principally using measurements of the channel impulse response and the total power therein to estimate the degree of dispersion in the time-multiplexed European “GSM” cellular-phone link. The effective dispersion time of the multiple reflected signals is computed, as is the time distribution of the total slot signal power. From this estimate, parameters of adaptive equalizers and/or maximum-likelihood (Viterbi-type) data decoders are adjusted to provide acceptable BER performance. To conserve power in battery-operated cell-phone transceivers, the degree of signal processing is dynamically minimized; when the channel is good, the extra processing hardware is switched off to extend battery life. This scheme is directed solely at time-division multiplexed systems (e.g., GSM) and is not broadly applicable to other types of systems such as spread-spectrum. Further, this patent makes no mention of PLL-based systems (single or multiple) and has no applicability to synchronization methods. Thus there is no commonality with the instant application.
U.S. Pat. No. 5,367,536, issued Nov. 22, 1994 to Ichiro Tsujimoto, describes a method in time-division multiple-access (TDMA) systems of transmitting concurrent sync and data bursts by differentially encoding the data to produce a spectral null near the RF carrier when modulated; conversely, the more bandlimited sync burst is directly modulated onto the carrier and thus occupies the spectral region immediately straddling the carrier frequency. Since the sync and data signal spectra are not overlapping, the receiver can separate out the sync components via a simple bandpass filter and recover a clean data-clock therefrom. In parallel, the data signal is corrected by a standard decision-feedback equalizer to filter out the sync components and subsequently demodulated; timing for these latter operations is obtained from the recovered sync-derived clock. This patent, although useful for its intended applications, does not involve any type of PLL circuitry and clearly employs very conventional techniques for extracting data clock from the received sync burst. No use of multiple PLL detectors or loops is mentioned. There is thus no overlap with the instant invention.
U.S. Pat. No. 5,838,741, issued Nov. 17, 1998 to Edgar Callaway, Jr. et al, discloses a scheme that ensures that digital data in an RF receiver is transferred to downstream stages only at times which will have minimal impact (e.g., from radiated or conducted noise) on the front-end and other more sensitive parts of the circuit. The scheme is generally applicable to miniature units and particularly relevant to single-chip (monolithic) devices. The salient goal is to minimize on-chip data transfers (with their inherent noise) during any critical signal-sampling instants, delaying them to less sensitive times. The system controller can be configured to insert an optimum delay into the various subsystem control lines to avoid logic transitions at noise-critical times for the various circuits. Although the techniques herein are useful for the manufacture of receiver hardware, they only deal with noise generated internal to the receiver itself and do not in any way address RF link noise and degradations affecting the input signal from the antenna. Thus this patent and the instant invention deal with totally different problems and therefore are not intersecting in scope.
U.S. Pat. No. 5,832,045, issued Nov. 3, 1998 to Andrew Barber, discloses a method and apparatus to adjust data-bit (baud) timing through a correlation assessment of intersymbol interference (ISI) induced by imperfections in the data link. This patent is directed at improved methods of generating baud (bit) timing for applications such as high symbol-rate data modems for telephone lines, where better precision in establishing bit timing is critical to high data throughputs with low errors. The invention improves timing resolution over existing carrier-envelope detection and simple bit-energy correlation methods by correlating successively adjacent (immediately leading and trailing) bits to provide a simple but accurate bipolar error signal which is then used to adjust the timing of the bit sampler which drives the correlators. This “early-late” scheme is similar in concept to spread-spectrum polynomial correlators widely employed in direct-sequence systems, but here simply functions as the phase-error detector in a conventional PLL setup. The application of this technique is never extended to recovering multiple clock frequencies, nor is the use of interconnected loops cited. Thus again, there is no commonality with the specifics of the instant case.
U.S. Pat. No. 5,825,805, issued Oct. 20, 1998 to Ichiro Kato, describes a spread-spectrum modulation/demodulation technique similar to the orthogonal frequency-division multiplex (OFDM) scheme used in European DV-B digital television transmission. The inventor claims the advantage of very rapid synchronization of the code at the receiver by matching the frequency-spreading pattern, but the patent discloses no specific PLL circuits or detectors to recover sync information; indeed, an advantage is cited in that existing-art sync and data demodulators can be utilized on the despread output streams. Thus, again, there is no overlap with the subject of the instant application.
U.S. Pat. No. 5,493,583, issued Feb. 20, 1996 to Peter Cripps, discloses a wireless transceiver architecture employing a PLL-based frequency-multiplier to generate the transmit carrier. The salient feature of the system is a means of rejecting simultaneously transmitted data in the same unit's receiver by subtracting a portion of the transmitted data bitstream from the received stream after demodulation to minimize transmitter-to receiver crosstalk. However, no use of multiple and/or crosscoupled PLLs is mentioned, and no synchronization functions other than common art are included. There is once more no conflict with the instant invention.
U.S. Pat. No. 3,633,115, issued Jan. 4, 1972 to Marvin Epstein, is a fundamental patent predating the chip-type PLL which discloses a means of following the average phase of an input clock signal for smoothing timing within a logic system. The PLL error signal is heavily filtered to ignore rapid phase variations or jitter in the input signal but faithfully track long-term trends. This concept, while incorporated in nearly all modern PLL implementations, is clearly in the public domain.
U.S. Pat. No. 4,780,891, issued Oct. 25, 1988 to Jean-Pierre Guerin et al, describes a method and apparatus to approximately phase-synchronize two digital bitstreams by using the later as a reference and inserting a programmable logic-generated delay (within a selectable control window) into the path of the earlier-arriving stream. This technique does not employ any PLL hardware and thus is not relevant to the instant case.
U.S. Pat. No. 3,491,338, issued Jan. 20, 1970 to Francis Malloy, discloses a receiver data synchronizer built around adjustable multivibrator timing elements. A predetermined multi-bit preamble is sent with each data burst to facilitate proper decoding and to provide discrimination against atmospheric noise. Adjustment of the system is essentially manual, and no PLL or other automatic correction mechanism is included.
U.S. Pat. No. 5,519,444, issued May 21, 1996 to Yong Ko et al, discloses a phase-synchronizing apparatus for digital audio signals in digital-video applications which regenerates a data transmission clock using a PLL topology. The various selectable clock-frequency sets (keyed to the standard 48-, 44.1-, and 32-kHz audio sampling rates) are generated from edges of the input digital-audio data pulses and two groups of programmable PLL-type frequency dividers, one driven by a 21.333-kHz master, reference clock and the other by an 18.432-kHz source. By selection of a multiplicity of the internal divide ratios, all the needed bit, frame, and sub-sampling rates for the 3 standard-rate digital audio streams can be generated. The two PLL systems are merely synthesizers and are cascaded to produce the desired frequencies, but they are not interconnected or used in an RF receiving function as in the systems of the instant invention.
U.S. Pat. No. 3,341,658, issued Sep. 12, 1967 to Hisashi Kaneko, discloses a matched-filter/correlator synchronization system for an RF receiver. This early development in correlation processing utilized tapped passive delay lines on the input and reference-waveform channels; the two signal sets were multiplied point-by-point and the sum used to correlate the received Barker-sequence encoded sync word with the identically encoded reference. At the peak of the correlation sum, the sync timing is probabilistically optimized, even in the presence of significant amounts of Gaussian noise. This patent, now obviously in the public domain, does not utilize multiple or interconnected PLLs of any kind and therefore does not impinge on the instant invention.
U.S. Pat. No. 4,545,061, issued Oct. 1, 1985 to Ronald Hileman, describes means for maintaining close receiver time synchronization in spread-spectrum and other correlation-type communication systems, even in low-SNR conditions. The basic sequence-correlation loop is equipped with a dithered local oscillator whose phase is perturbed periodically; the resulting dither modulations on the heterodyned received signal are coherently detected in a switched phase-inverter run at the same dither rate. The resulting dither-sideband energy is sent to two antiphase high-Q resonators, which are subsequently amplitude-detected in a diode bridge and low-pass filtered. The resulting bipolar error signal is then used to adjust the local correlator clock, which in turn tracks the received sequence phase and thereby achieves synchronization with what is conventionally known as a “tau-dither” loop. Since only one PLL is utilized, this patent does not relate to the instant case.
U.S. Pat. No. 5,402,450, issued Mar. 28, 1995 to Gary Lennen, discloses a complex scheme to subtract out multipath-induced errors from the satellite-based positioning signals received in a GPS receiver. In general, good multipath rejection is difficult to achieve except in spread-spectrum or other dispersive communications systems; even in these formats, multipath causes noticeable degradations in overall system performance. Succinctly, this technique is based on an understanding of the autocorrelation function (AF) of a spread-spectrum signal. In an ideal case, the AF is triangular when plotted against code-signal delay. The presence of multipath components in the received signal distorts and delays the peak of the AF (best correlation point), which causes an error when the AF is employed in a delay-lock loop (a form of PLL) to measure the precise code phase (and thus the pseudorange) from a GPS satellite. Although the implementation incorporates multiple delay-lock loops, they are operated in parallel and employ individual detectors for each loop; as a result, this patent does not overlap with the instant invention.
Finally, U.S. Pat. No. 5,739,727, issued Apr. 14, 1998 to Bjõrn Lofter, et al, discloses a sampled PLL being locked with support from another (standard) PLL. The application is in a programmable frequency synthesizer which is desired to have fast switching and settling times and simultaneously exhibit low phase noise in the locked condition. Since in conventional PLL circuits, a fast response time requires a large control-signal bandwidth, this constraint is directly at odds with a low phase-noise level (requires heavy control-signal filtering and thus low bandwidth). The solution in this patent is, after switching the synthesizer to a new frequency, to pre-set the main PLL's initial frequency (using a fast digitally-sampled auxiliary PLL) to the desired value, thus affording rapid switching. To maintain the desired low phase noise, the main-PLL control voltage is severely filtered to limit its bandwidth; now that the main PLL control voltage is preset by the “helper” circuit to very close to its desired final value, the slow main-loop response will not degrade the system's overall switching/settling time specs. This concept, however, does not address receiver applications or multiply-interconnected PLLs; thus it is completely distinct from the instant invention.
While each of the foregoing may have some utility for the intended applications thereof, none of them directly address or effectively solve the problems noted initially above. For these reasons, there still remains room for improvement in the art.